The present invention relates to a charge pumping circuit, and more particularly to a charge pumping circuit in which the layout and current consumption are improved by reducing the number of simultaneously operating charge pumps in a DRAM.
Typically, during the operation of a DRAM various voltages are utilizing. The DRAM is equipped with a charge pumping circuit which detects the level of a supplied voltage and which pumps the voltage in order to maintain a predetermined voltage level.
A DRAM cell can use a high voltage Vpp or a back bias voltage Vbb upon operation of the cell, and the DRAM cell is equipped with a distinct charge pumping circuit for the purpose of supplying the high voltage Vpp or the back bias voltage Vbb.
The high voltage Vpp can be used for read and write operations of the DRAM cell. A typical circuit used for pumping the high voltage Vpp is shown in FIG. 1.
The charge pumping circuit of FIG. 1 includes a high voltage sensor VPP SENSOR 10, a high voltage oscillator 12, and high-voltage pumps VPP Pump 14 which receive pulse signals outputted from the high voltage oscillator 12.
Herein, the high voltage sensor 10 detects the level of the high voltage Vpp and generates a control signal if the level of the high voltage Vpp decreases to a predetermined level. The control signal generated by the voltage sensor enables pumping to restore the high voltage Vpp to the desired level. The control signal output by the high voltage sensor 10 has either a high or low level.
The high voltage oscillator 12 receives the control signal from the high voltage sensor 10 and generates a clock signal OSC using an internal oscillating operation when the control signal is in an enabled state. The clock signal OSC outputted from the high voltage oscillator 12 has a predetermined period and a predetermined pulse width. Also, the high-voltage oscillator 12 is configured with a ring oscillator, in which a plurality of inverters forms a closed-loop chain.
The high-voltage pumps 14 are disposed in a plurality of regions (region 1, region 2, region 3, in FIG. 1) where the high voltage must be supplied. The number of the high-voltage pumps 14 for each region can be determined according to the drive capability requirements of the corresponding region. As shown in FIG. 1, three high-voltage pumps 14 are disposed in region 1, six high-voltage pumps 14 are disposed in region 2, and four high-voltage pumps 14 are disposed in region 3.
Each high-voltage pump 14 in each region receives the clock signal OSC having the same period and pulse width from the high voltage oscillator 12, and each high voltage pump 14 pumps the high voltage Vpp in synchronization with the clock signal OSC to supply the high voltage Vpp to an element (e.g., sense amplifier) of the corresponding region.
As a result, in the conventional charge pumping circuit shown in FIG. 1, each of the high-voltage pumps 14 are operated simultaneously in response to the single pulse signal OSC in order to pump the high voltage Vpp.
If large numbers of high-voltage pumps operate at the same time, large amount of current is consumed, and thus the peak current is extremely high. When a charge pump of high voltage Vpp is utilized (thereby resulting in a large amount of consumed current), current from the external supply voltage VDD is also consumed, and therefore in a typical circuit for pumping the high voltage Vpp the operational characteristics of a DRAM are deteriorated.
Further, the large number of high-voltage pumps configured in the typical circuit of FIG. 1 has a disadvantage in terms of the layout of the circuit.